Low-Power Approximate RPR Scheme for Unsigned Integer Arithmetic Computation

A scheme often used for error tolerance of arithmetic circuits is the so-called Reduced Precision Redundancy (RPR). Rather than replicating multiple times entire module, RPR uses reduced precision (inexact) copies to significantly reduce redundancy overhead, while still being able correct largest errors. This paper focuses on low-power operation RPR; a new proposed. At circuit level, power gating initially utilized in modules off one (i.e., exact module) when inexact modules’ smaller threshold. The proposed design applicable (unsigned integer) addition, multiplication, and MAC (multiply add) by proposing implementations that consumption with limited impact its correction capability. schemes have been implemented tested various applications (image DCT processing). results show they can consumption; moreover, simulation Mean Square Error (MSE) at schemes’ output low.